The gate-all-around (GAA) transistor design used in Samsung Electronics’ 3-nanometer (nm) manufacturing node, the market leader in semiconductor technology, has begun initial production.
Samsung’s GAA technology, Multi-Bridge-Channel FET (MBCFETTM), overcomes the performance restrictions of FinFET by increasing performance by increasing drive current capability while simultaneously increasing power efficiency by lowering the supply voltage level.
With semiconductor chips for high-performance, low-power computing, Samsung is launching the first use of the nanosheet transistor and has ambitions to expand to mobile CPUs.
“Samsung has expanded quickly as we continue to show leadership in integrating next-generation technologies into production, including the first High-K Metal Gate in the foundry sector, FinFET, and EUV. With the introduction of the MBCFETTM, the world’s first 3nm process, we hope to maintain our position as industry leaders, according to Dr Siyoung Choi, president and head of Samsung Electronics’ foundry business. “We will continue actively innovating in the creation of competitive technology and create procedures that aid in accelerating the maturation of technology.”
Optimization of Design and Technology for Maximum PPA
In contrast to GAA technologies, which use nanowires with smaller channels, Samsung’s patented technique uses nanosheets with broader channels, enabling higher performance and improved energy efficiency. Samsung will be able to modify the channel width of the nanosheet using the 3nm GAA technology in order to optimise power consumption and performance to satisfy diverse client demands.
Additionally, Design Technology Co-Optimization (DTCO), which enhances Power, Performance, and Area (PPA) advantages, benefits greatly from the design flexibility of GAA. First-generation 3nm processes have power consumption reductions of up to 45%, performance enhancements of up to 23%, and area reductions of up to 16% when compared to 5nm processes. Second-generation 3nm processes have power reductions of up to 50%, performance enhancements of up to 30%, and area reductions of up to 35%.
Infrastructure & Services for 3nm Design with SAFE Partners
IC designers confront issues processing enormous volumes of data to test complicated devices with more functionality and tighter scalability as technology nodes get smaller and chip performance demands expand. To address these needs, Samsung works to make the design environment more stable in order to speed up the design, verification, and sign-off processes and increase product dependability.
Since the third quarter of 2021, Samsung Electronics has worked diligently to prepare the Samsung Advanced Foundry Ecosystem (SAFE) partners, including Ansys, Cadence, Siemens, and Synopsys, to provide proven design infrastructure to help customers perfect their products more quickly.