Samsung Electronics

Samsung Electronics, a leading global in advanced semiconductor technology, today announced HybridSubstrate Cube (H-Cube) technology, it’s own latest 2.5D semiconductor packaging option special for HPC, AI products, networking, and data centre requirements which necessitate large-scale packaging technology.

“In today’s environment, at which systems integration is becoming more important as well as surface supplies are becoming scarce, Samsung Foundry and Amkor Technology have successfully developed the H-Cube code to overcome this challenge,” stated “ JinYoung Kim, vice president of Amkor Technology’s Global RandD Center. “That invention lowers the entrance hurdle into the HPC/AI sector and illustrates a successful collaboration and partnership between both the foundry and the Companies outsource Semiconductor Running tests and Assembly (OSAT) firm.”

Structure and Functions of the H-Cube

In a compact form factor, the 5D package allows users to install logic chips or high bandwidth memory (HBM) on top of a silicon supplements. Samsung’s H-Cube system involves a hybrid platform with a fine pitch platform capable of fine bump connections and a high density interconnection (HDI), allowing huge sizes to be implemented in a 2.5D packaging. Large-area packaging is becoming more significant when the quantity & size of chips put in a package grows or increases, as the consider in the HPC, AI, and network application market sectors have recently increased. It is necessary to have high-speed broadband communication. Fine pitch substrates are required for the attachment and connecting of silicon chips, including the interposer, but their costs rise significantly as the size grows.

Concept of H-Cube™ Package Structure

If six or more HBMs are combined, the challenge of creating the huge substrate grows quickly, lowering efficiency. Samsung resolved the challenge by using a hybrid substrate structure that combines easy-to-process HDI substrates with a high-end fine-pitch platform over a large expanse. Due to a 35 percent reduction in solder ball pitch, that electrically links the chip and platform, the size of the fine pitched platform may be reduced, while an HDI substrate (PCB module) can be added beneath the fine pitch substrate for secure interaction with the board system. Furthermore, in order to increase the H-Cube solution’s dependability, Samsung’s unique power and signal integrity analysis technology has been used to deliver steady power while reducing signal loss or distortion while stacking numerous logical and HBM chips.

This industry-leading five-layer EUV process gives Samsung the highest bit density DRAM on the market, resulting in a 20 percent improvement in productivity over the latest DDR5 standard. Using Samsung’s 14nm DRAM, AI workloads and 5G workloads can be handled efficiently.

The world’s leading memory company, Samsung Electronics, today announced the advent of its ultra-thin, nanoscale 14 nanometer (nm) high-speed DRAM, manufactured with EUV technology. The industry’s first EUV DRAM was delivered last March by Samsung, and Samsung has now increased layer counts to five so that its products are built with the most robust and advanced DRAM processes available today DDR5. Senior Vice President and Head of DRAM Products and Technologies at Samsung Electronics.

Today, Samsung is taking a new technological step forward with the multilayer UVV which has enabled extreme miniaturization at 14nm, a feat not possible with the conventional argon fluoride (ArF) process.  this advancement we will continue to provide more differentiated memory solutions by fully addressing the need for better, more capable cities in the data-driven world of 5G, artificial intelligence and metaverse. As DRAM continues to expand the 10nm range , EUV technology is becoming more and more important to improve the accuracy of models for higher performance and yields. 

With five EUV layers at its 14nm DRAM, Samsung has achieved the highest bit density while improving overall productivity wafers by about 20% The 14nm process can help reduce power consumption by up to 20% compared to the previous generation DRAM node.

Taking advantage of the latest DDR5 standard, Samsung’s 14nm DRAM will help unlock unprecedented speeds of up to 7.2 gigabits per second (Gbps), more than double the DDR4 speed of up to 3 , 2 Gbit / s. Samsung plans to expand its 14nm DDR5 portfolio to support enterprise data center, supercomputer and server applications. Additionally, Samsung plans to increase the density of its DRAM chip from 14nm to 24GB to better meet the rapidly growing data demands of global computer systems.

 Four high-performance, low-power chips have won the Carbon Trust label for measuring product carbon emissions, paving the way for reducing carbon emissions.

Samsung’s Green Manufacturing Efforts Continue to Expand Product Range Samsung Electronics, a global leader in advanced semiconductor technology, announced today that four LSI products have received the Carbon Trust Product Carbon Footprint Label, the first Samsung logic chip to do so. With the Semiconductor Industry’s first carbon certification for memory chips from the Carbon Trust in 2019, Samsung has expanded its ESG (Environment, Social and Governance) spectrum by globally recognizing its green logic chip.

Samsung also achieved the Carbon Trust’s first three industry standards for carbon, water and waste in June 2021. World advises companies on their capabilities in a sustainable manner. The Carbon Trust also measures and certifies the environmental impact of organizations, supply chains and products. Among the various certification categories of the Carbon Trust, Samsung Systems LSI products have received a CO2 label.

Samsung ElectroMechanics announced on the 12th that it has developed two types of automotive MLCCs, which are part of Advanced Driver Assistance Systems and # 40; ADAS ‘, a safe driving system essential for autonomous vehicles. (MLCC) is the main component of electronic devices that control the steady-state current in the circuit of electronic products and is required for smartphones, home appliances and cars.

recognize and assess possible situations during autonomous driving, including lane keep assist & # 40; LKAS & # 41; Surround View Monitor (SVM) and Intelligent Cruise Control (SCC). As vehicle functions improve, the number of semiconductor and high-performance components installed inside the vehicle is gradually increasing. In particular, the requirement for a self-propelled vehicle with a reliable power supply (source) and noise cancellation capability for various ICs to receive the signal quickly also requires small size and high MLCC capacity.

Due to the lack of installation space with the increase in the number of components. size 0603 (width 0.6mm, length 0.3mm) and capacitance 100nF (nanofarad) and also high power product with 3216 (width 3.2mm, 1.6 mm) and a capacity of 47 μF (microfarads). ※ 1 μm (micro) = 1000 n (nano) MLCC 0603 delivers the same 100 nF (nanofarad) power as 1005, with a 64% reduction in surface area compared to size 1005 (1.0 mm width, length 0.5 mm). This product is installed on the signal head of the vehicle’s electronic control unit (ECU) to eliminate interference from ambient signals and accurately transmit the signal. In addition, the new product has twice the flexural strength of the standard product, which prevents the MLCC from being damaged by shocks and vibrations while driving, increasing product reliability. Specifically, the product complies with AECQ200, the automotive electronic component reliability test standard, so it can be used not only in ADAS but also in other applications such as body, chassis and infotainment system.