During the IEDM conference in San Francisco, Samsung and International Business Machines (IBM) unveiled a revolutionary transistor stacking architecture. One of the driving forces behind the emergence of computers, as well as the world’s top smartphone manufacturer, has teamed up with one of the world’s major chip manufacturers and general electronics manufacturers. The revolutionary semiconductor architecture will be realised by vertically stacking transistors on a chip.
Samsung and IBM hope to push Moor’s Law beyond the nanosheet level while using less energy. It will double the performance or use 85% less power than processors that employ existing FinFET transistors, according to the two titans.
These firms are among the first to make the new technology public. They aren’t the only ones, though. Intel, another chip industry behemoth, is developing chips that can be stacked on top of each other to save space. Intel also wants to shorten interconnects and conserve energy in order to build processors that are more cost-effective and perform better. By 2024, Intel hopes to have completed the design for angstrom-scale processors. It will be used in the “Intel 20A” node and RibbonFET transistors from Intel.
This new design promises smartphones with one-week battery life and energy-efficient crypto-mining.IBM and Samsung, for example, are making strong promises about the benefits of such technologies. The new standard, according to the businesses, might one day allow cellphones to last a week on a single charge. In a world where we have to charge super-expensive devices on a regular basis, that’s rather astounding. According to the business, certain energy-intensive processes, such as crypto mining, might be made more energy-efficient. As a result, they would have a lower environmental effect.
Unfortunately, neither IBM nor Samsung have stated when the design would be available for purchase. However, we believe it will be a few years before this becomes a reality. After all, we’ve only recently passed through the 4-nanometer node. Companies are still expected to test 3nm and 1nm before cracking the barrier.
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